1. Field of Invention
This invention relates to improvements in methods for making or synthesizing logic circuits of the type that use domino logic circuits and principles.
2. Relevant Background
Recently, domino logic circuits and design have been receiving the attention of logic circuit designers and fabricators. Domino logic is a precharged, non-inverting family of Complementary Metal Oxide Silicon (CMOS) logic that uses multiple clock phases to effect high-speed operation. Domino logic is faster than standard static logic, but it is more difficult to design because of its increased complexity, primarily in the clocking network.
Typically in domino logic, at least a “precharge” clock phase is used, followed by an “evaluate” clock phase. During the precharge phase, when the clock is low, the output of the cell goes low. During the evaluate phase, when the clock is high, the output of the cell can only transition from a low to a high value. This is in contrast to standard static logic typically used with CMOS technology. In static logic designs, the output of the cell can rise or fall, depending on the input conditions, during normal operation.
Skew-tolerant clocking can be applied to either static or domino logic. Skew-tolerant clocking requires three or more overlapping clocks to be supplied to the design.
In the fabrication of static and domino logic designs, various synthesis techniques may be employed. In general, synthesis refers to a method by which a gate level logical implementation of a design is generated based on a high level functional description. “Gate level” is used herein to refer to a logic function level, such as an AND function, OR function, etc, rather than at a gate level as a part of an individual MOS device component.
Logic synthesis is usually carried out using logic optimization and technology mapping. Logic optimization refers to optimizing and reducing the logic in a technology independent manner. Technology mapping refers to an optimal mapping, based on some cost function such as timing, of the cells in a library to the logic.
Microprocessor performance in recent years has significantly exceeded predictions made as late as 1997 in the Semiconductor Industry Association (SIA) roadmap. The increased performance of microprocessors can be attributed to their deeply pipelined microarchitectures and their increased utilization of sophisticated design styles, led primarily by domino logic. With the application of better methodologies (primarily microarchitectural, such as pipelining and logic design) in ASIC design, it has been suggested that domino logic is becoming the primary differentiator between custom and ASIC design styles. This indicates the continued use of domino logic in custom designs, as well as the increasing competitive benefits in using domino logic modules for critical paths in more general design methodologies.
A primary limitation to using domino logic has been the need to employ time-consuming custom design implementation techniques to construct domino circuits. While such design techniques can lead to high performance implementation, with the exception of microprocessor and high-end computational units, the techniques are not cost or time effective for most market segments. For lower-end circuits, on the other hand, the automatic synthesis of static logic has become a standard design technique.
The difficulty in synthesizing domino logic relates to two major differences between the design styles of domino and static logic modules. First, domino logic is non-inverting. This implies that no inverters or other inverting cells can be used in the synthesis process. Many commercial synthesis techniques will only synthesize a circuit from a library that contains an inverter. Second, domino logic operates alternately in the precharge and evaluate modes. Consequently, the clocking system in domino logic must mask the dead time during cell precharge in order to ensure that it is not added to the critical path delay. This requires a relatively extensive and complex clocking system.
The benefits of using domino logic have led to a number of proposed solutions to the synthesis problems. Many of the proposals concentrate on solving the first problem mentioned above, namely, to build the logic function with non-inverting cells. However, these solutions generally have at least three practical limitations from an industrial perspective.
First, the work on domino synthesis frequently involves the development of synthesis tools. Most semiconductor companies do not wish to become involved in the complex and burdensome task of supporting a synthesis tool. Second, previous work on domino synthesis generally does not deal in detail with the clocking scheme. Third, previous work on domino synthesis is unclear about the definitions of or distinctions between the static and domino regions. The basic assumption is that the logic will be implemented with both static and domino gates. While the problem is interesting, especially in academia (optimal partitioning is a large and active research area), it is currently of limited utility in practical applications. This is because a domino-to-static interface requires the domino values be latched, which adds complexity and delay if robustly done. Also, experience has shown that the static logic slows down the overall circuit module. While we wish to mix static and domino logic, our goal is for this to be done with static cells seamlessly with domino cells, without separate regions constituting domino only and static only cells.
One method which has been employed for synthesizing domino logic begins by mapping an RTL circuit description to a set of AND gates, OR gates, and inverters. The inverters are then pushed towards the inputs by recursively applying DeMorgan's Law to any inverter at the output of a logic device. This procedure is called “bubble-pushing”. At the end of bubble-pushing most of the inverters will have been moved to the primary inputs, except those which are trapped in the circuit. Sometimes, for example, inverters become trapped when both an inverted and an uninverted version of an internal signal are needed. Some of these trapped inverters can be removed if they drive different outputs by changing the output phase of signals. This is acceptable since the signal can be easily inverted in the output flip-flop. This procedure is called “output phase optimization”.
At the end of output phase optimization, some inverters may still be trapped in the network. These signals are generated by providing the input fan-in cone for them starting at the primary inputs to the circuit. These cells are in the binate region of the logic, which may be redundantly implemented. The other cells are part of the unate region, in which no inverting logic is present. This logic is directly mapped to single rail domino cells.
While this procedure leads to functionally correct domino implementations, it does have certain limitations. First, all logic mappings after the first are limited to technology mappings and drive strength changes. Allowing a plurality of global mapping passes may lead to the inclusion of inverters in the logic, which is not acceptable. Synthesis of arbitrary functions to only inverters, AND gates, and OR gates leads to sub-optimal implementations compared to directly mapping the design to a larger library. Second, a number of technology mapping passes needs to be performed for the binate regions, the unate regions, and the input inverters. The logic then needs to be reassembled. Finally, since many commercially available synthesis tools will not synthesize logic unless an inverter is in the library, often a dummy inverter has to be incorporated in the library. In order to ensure that the dummy inverter is never used, it is assigned an extremely large area and delay. Nevertheless, despite these efforts, the dummy inverter is nevertheless sometimes incorporated into the design, rendering the entire circuit design useless. It is also uncertain how the inclusion of such circuits which are in the library but not intended to be used affects the quality of synthesis.